Integrated circuit design and manufacture involves a multitude of steps, many of which are commonly performed using electronic design automation (EDA) tools running on a computer. Frequently, millions and even hundreds of millions of electronic devices, such as transistors, capacitors, resistors, and conductors, can exist on a single semiconductor chip. Each electronic device is composed of features, such as diffusion features, polysilicon features, contacts, metallization features, and other structures on a semiconductor die, each having various shapes and electrical characteristics. A layout design for an integrated circuit provides shapes for many different mask layers that are used to create the various physical features.
As technologies have advanced, smaller and smaller dimensions, or feature sizes, must be produced during the semiconductor production process in order to allow many more electronic devices to be created in the same amount of space on a semiconductor die than was formerly possible. Typically, some type of photo-lithography is used to create structures on the chip. One photo-lithographic technique for forming a set of structures in a particular layer of a chip is to deposit a layer of material on the chip and then to coat the layer with a photo-sensitive material. A light is then shined through a mask in which various shapes have been cut which, when the light is shined through the shapes, selectively expose desired patterns on areas of the photo-sensitive material not covered by the shapes in the mask. The exposed areas of the photo-sensitive material, along with the layer of material below those exposed areas in some cases, are then etched away. After the unexposed photo-sensitive material is removed, the desired structures remain.
As the feature sizes of integrated circuits have gotten smaller, in some cases even smaller than the wavelengths of the electromagnetic radiation (EMR) used in the lithographic processes, the challenge of fabricating features has forced the development of various techniques, such as multiple pattern lithography, which allow the creation of physical features that do not correspond to the shapes of any single mask layer. In some embodiments of double pattern lithography, the simplest variant of multiple pattern lithography, a line of sacrificial material is created, using a mask, on top of a layer of material to be patterned. The line of sacrificial material is covered with a spacer material and then the horizontal portions of the spacer material are etched away, leaving spacer material on the sides of the line of sacrificial material. The line of sacrificial material itself is then removed, leaving two lines of spacer material on top of the material to be patterned for each line of material that was created using the mask layer. The material to be patterned can then be etched, with the material under the lines of spacer material untouched, to create the patterning. The spacer material is then removed, leaving final features in the physical semiconductor chip that have no directly corresponding shapes in the layout design layers.
To perform some types of design analysis, such as failure analysis, actual physical structures on a semiconductor chip are examined to determine if the shapes were fabricated properly. If the fabricated structures correspond to shapes in a mask, it can be relatively easy to determine if the fabricated structures were created properly, simply by comparing the fabricated structure in question to a shape of the layout design. But if the fabricated structures do not directly correspond to shapes in one of the mask layers, it can prove much more difficult to determine if a physical structure has been created properly.